Verilog, random stimulus, VMM, Uvm, assertion-based verification, functional coverage, advanced verification methodologies, systemverilog

Gate Level Simulation (GLS), Verilog, Matlab, Python, Adaptive filters, Digital design concepts, Analog and Channel model development, FPGA-based emulation, Sampling, Filters, FPGA emulation, modulation, DSP concepts, system modeling

Perl, Ruby, System Verilog, make, Uvm, Asic verification, Rtl Design, formal verification, TestBench Development

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification

Verilog, cdc, VHDL, RDC, Test plan creation and execution, Formal verification methodologies, Uvm, Constrained random verification techniques, systemverilog

DDR, Pcie, Perl, Vcs, Python, Tcl, Uvm, Axi, Verdi, APB, Questa, systemverilog