C, Verilog, Scripting, RTL testbench debug, interconnects, Arm-based SoC architecture, memory hierarchy, Uvm, UPF, systemverilog, coverage closure, coherency

Usb, Vcs, DDR, Perl, Pcie, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog, CXL, LPDDR, high-speed protocols

rtl verification , Debugging, AMS IP Verification, AMS IP Integration, SoC-Level Verification, Sub-System Verification, PDL Test Case Development, Gate-Level Simulation, Timing Simulation, Virtual Tester Simulation, Tessent DFT, DFT Pattern Generation, Pattern Simulation, Testbench Bring-Up

C, Shell, Perl, Verilog, System Verilog, Python, Cadence Tools, Xcelium, Uvm, safety simulator, VHDL, vManager, Formal applications

DDR, Shell, Pcie, Perl, Python, JESD204B, Uvm, UPF, GLS, systemverilog, MIPI, Dft, USB3

Perl, Python, SV, low power simulations, Uvm, testbench development, debugging gate level simulations, assertions coding

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Uart, Usb, Regression Testing, C Programming, Ethernet, SVA, Assertions, Uvm, UPF, Functional Coverage, systemverilog, AMBA Protocols, AHB, CPF, APB, Axi, ARM-based SoC Verification