Gate Level Simulation (GLS), Verilog, Matlab, Python, Adaptive filters, Digital design concepts, Analog and Channel model development, FPGA-based emulation, Sampling, Filters, FPGA emulation, modulation, DSP concepts, system modeling

Verilog, System Verilog, Coverage Closure, Assertion Checker Development, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging

Perl, Ruby, System Verilog, make, Uvm, Asic verification, Rtl Design, formal verification, TestBench Development

System Verilog, SV UVM based test benches, scripting languages such as Perl, HDLs like Verilog, debugging RTL TB issues using Verdi or similar tools

Verilog, Python, Synopsys, low power design techniques, performance modeling tools, bus architectures, Cadence Tools, accelerators, memory hierarchies, arithmetic units

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification

DDR, Pcie, Perl, Vcs, Python, Tcl, Uvm, Axi, Verdi, APB, Questa, systemverilog