Clock Tree Synthesis (CTS), Unix, Linux, Perl, CTS optimization, Low power verification, Asic Design Verification, floorplanning, Placement, power analysis, PNR implementation

Routing, IR Drop Analysis, Synthesis, ICC Innovus, Extraction, floorplanning, Placement, P R skills, Signal Integrity, Power Physical Verification, GDSII

Soc, Scripting Languages, LVS, power plan, UPF, Place Route, Tweaker, PrimeClosure, Cadence Tools, STA flow methodology, ESD analysis, Floor plan, primetime, Tempus, IP level Synthesis, analog digital interface, formal verification, ERC, IO ring, DRC

Soc, Pvs, Tcl, Designing

Tcl Scripting, RTL synthesis, Conformal, Synopsys Fusion Compiler, LEC, VCLP, UPF, Cadence Genus