Uart, Spi, Jtag, Perl, Pcie, I2c, Python, Tcl, Synthesis, Emulation, FPGA prototyping, board bring-up, multi-FPGA partitioning, ZeBu, Protium, Timing Closure, Veloce, system-level debug, MDIO, HAPS, bitfile generation

boundary scan , Jtag, Perl, Python, Tcl, LINT, ASIC design flow, DFT DRC, cdc, Analog DFT, MBIST, Scan compression, Scan stitching, Dft, Low power DFT Techniques, ATPG, Low Power Checks, RTL Coding, ATPG Coverage improvement, LBIST, DFT STA Constraint development

Linux Kernel Programming, Board Support Package, Svn, JIRA, Git, Emulator, Yocto, Linux Device Drivers, Qualcomm, JTAG programmer, NVIDIA, protocol analyser, NXP, embedded microprocessor, Buildroot, Intel, TI, Oscilloscope, boot loader development, Signal Generator, Linux Kernel Internals

Perforce, Artifactory, HTML, Jtag, Javascript, Python, CSS, PowerShell, SQL Server, Visual Studio, Msbuild, Jenkins, Git, Arm Assembly, ASP.NET, Rest Apis, Windbg, Microsoft Devcenter, HLK, E2E External Releases, MSI generation, Production signed Releases, INX, CMD, CID, VCXProj, HID, WIX Tools, ATT Signing, Windows OS internals, BAT, Device driver debugging

boundary scan , logic bist , DFT techniques, Memory BIST, IDDQ, Bridging fault generation, Pin-muxing, At-speed Path delay, SDD, At-speed Scan Test-clocking, Scan On-Chip Compression, Test vector Stuck-at, Analog Testing, on-chip compression, high test coverage, timing SDF, Scan Insertion, Test Modes implementation and verification, simulations at gate level

power supplies , test automation, Debugging Tools, Jtag, Embedded C, Serial Wire Debug, low-level device drivers, protocol analyzers, logic analyzers, Oscilloscopes, Git-based version control, multimeters, boot sequences, Diagnostics, communication interfaces

Perl, Verilog, Python, Rtl Design, digital design fundamentals, micro-architecture development, design simulation and debug tools, computer architecture concepts, systemverilog

rtl development , static timing analysis, Verilog, Digital Signal Processing, LINT, Synthesis, Debug, LEC, Simulation, Matlab modeling, FPGA prototyping

Physical Design, Timing optimization and closure, Timing Closure, Physical verification and signoff checks, floorplanning, EDA tools for physical design verification, Low-power design methodologies, Package co-design, Static and Dynamic IR drop analysis, Power grid design, Placement and routing