C, Vcs, Verilog, Perl, spyglass, formal verification, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

multi-domain clock synchronization, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, high performance memory subsystems, ASIC debugging

Ethernet, Fcoe, Verplex LEC, networking ASICs, high-speed serial interfaces, ASIC Design, high-performance memory subsystems, Synopsys Design Compiler, multi-clock domain synchronization, Verilog RTL coding, spyglass

C, Vcs, Verilog, Perl, formal verification, spyglass, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

code coverage , Verilog, System Verilog, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, AHB, ip development, functional coverage, front-end design tools

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture