boundary scan , Jtag, Scan Insertion, SoC Netlist level DFT execution

Sta, silicon debug, timing annotations, DFT methodologies, MBIST, ATPG patterns, IEEE 1687, DFT Architecture Strategy, Physical Design, Scan ATPG, LBIST, DFT timing constraints, IJTAG

Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Design for Test methodologies, Mentor testkompress

Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC Coverage debug, Scan Insertion