Scripting, RTL-to-GDSII Execution, SoC-Level Physical Design, Cross-Functional Collaboration, Timing PPA Closure, Architecture Methodology, SerDes IP Integration, Team Leadership Mentorship, Technical Ownership Project Planning, Stakeholder Vendor Alignment, Advanced Technology Nodes, Risk Issue Management, EDA Tool Proficiency

Ecos, Python, Perl, Tcl, Sta, CTS, Antenna, Cadence Innovus, LVS, routing optimization, congestion optimization, routing issues, SDC, MMMC, advanced technology nodes, full-chip physical implementation, constraint development, floorplanning, PPA improvements, EM, Ir, Timing Analysis, signoff, setup hold closure, SI crosstalk, DRC, Timing Closure, complex SoC designs, Placement

Tcl Scripting, Shell scripting, Python, Routing, Perl, Sta, Signoff, CTS, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Signal Integrity, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2

Routing, power analysis, Physical Verification, Physical Design, floorplanning, Timing Closure, Placement, DRC, LVS, Signal Integrity, Rtl Design

Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog

routing, Sta, CTS, ASIC PD methodologies, digital design fundamentals, Extraction, Floor Planning, PNR, Placement, EM IR closure, signoff

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation

power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies