Unit Testing, Uart, Ethernet Protocols, Spi, I2c, Logic Design, ASIC design flow, Synthesis, digital design concepts, Communications, gate level simulations, high speed design, backend, functional safety design, MIPI, Synthesis, Verification, HDMI, Timing, LINT, front end implementation tools, Equivalence Check, cdc, DP, Sta, ASIC synthesis constraints, Power estimation tools, IP level verification

pipelining , Perl, Verilog, Debugging, Python, Tcl, Synthesis, Timing Analysis, datapath design, digital IP development, systemverilog, Rtl Design, low-power design concepts

Usb, Spi, JIRA, Jenkins, DDR, Bitbucket, Pcie, Perl, Verilog, Ethernet, I2c, Python, timing optimization, micro-architecture design, Synthesis, coverage analysis, eSPI, LPDDR4, FPGA-based emulation platforms, assertions, RTL logic design, I3C

Sta, RTL2GDS, EDA Tools, Timing Analysis, Physical Design

Sysinternals., Windows Internals, Powershell Scripting, automation, Splunk, Wireshark