occ, Memory-BIST, DFT architecture scan Insertion compression at core level and SoC level, SSN architecture, timing and no-timing simulations, clock architecture, ATPG pattern generation coverage analysis

boundary scan , Jtag, cdc, Digital design fundamentals, Low Power Checks, LINT, ASIC design flow, Analog DFT, RTL Coding

automation, Scripting, scan compression, BSCAN, MBIST, Siemens Tessent, SSN TestKompress, DFT architecture, ATPG, EDA Tools, Synopsys TetraMAX, DFTMAX, LBIST, IJTAG

Vcs, Perl, Python, Tcl, ATPG Fault Models, DFT Debugging, Siemens Tessent, Synopsys TestMAX, End-to-end DFT implementation, RTL SoC Design Flow, Cadence Modus, STA Timing Closure, MBIST LBIST, DFT Sign-off Fault Coverage, JTAG Boundary Scan – IEEE 1149.1, Scan Insertion Compression

boundary scan , Jtag, PLL testing, Memory BIST, Post-silicon debug, ATE correlation, Power-on self-test, systemverilog, UVM testbench development, Phy Loopback, Formal verification methods, Clock control verification, SSN compressed scan, Silicon bring-up

Perl, Verilog, Python, Tcl, MBIST, Pre-Silicon test planning, Scan Insertion, low power concepts, DFT test suite development, RTL design for DFT, power gating, clock gating, DFT methodologies, SSN, systemverilog, SoC Level DFT Integration, TPI, DFT Compiler, Siemens Mentor Tessent, ATPG, Synopsys TetraMAX, Scan, IJTAG