C, Verilog, Scripting, RTL testbench debug, interconnects, Arm-based SoC architecture, memory hierarchy, Uvm, UPF, systemverilog, coverage closure, coherency

Usb, Vcs, DDR, Perl, Pcie, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog, CXL, LPDDR, high-speed protocols

arm architecture , C, Ovm, Jtag, Perl, Verilog, Python, System Verilog, CPU architecture, interconnects, Uvm, power management techniques, debug architecture protocols, coherent fabrics, VHDL, SoC Verification, SVTB

rtl verification , Debugging, AMS IP Verification, AMS IP Integration, SoC-Level Verification, Sub-System Verification, PDL Test Case Development, Gate-Level Simulation, Timing Simulation, Virtual Tester Simulation, Tessent DFT, DFT Pattern Generation, Pattern Simulation, Testbench Bring-Up

Perl, Python, SV, low power simulations, Uvm, testbench development, debugging gate level simulations, assertions coding

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Uart, Usb, Regression Testing, C Programming, Ethernet, SVA, Assertions, Uvm, UPF, Functional Coverage, systemverilog, AMBA Protocols, AHB, CPF, APB, Axi, ARM-based SoC Verification

arm architecture , Test Plans, C, C++, ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, PCIe Controller PHY IPs and protocols, DDR protocols, pre-silicon SoC verification, Memory Controller PHY IPs, performance verification, Coverage, checkers, Emulation, test generators, test benches