Python Scripting, System Verilog, debug tools, Visa Trace Observability, Trigger TAP based functional testing, Pre silicon validation, Xeon Debug fabrics, UVM Verification

Unix, Linux, Perl, Shell scripting, Python, Functional Coverage, Assertions SVA, Emulation Platforms, Palladium, Uvm, RTL Debug, systemverilog, ZeBu, Veloce

lauterbach , Spi, C, Systemc, Usb, Shell, Tcl, Verilog, Jtag, Python, Pcie, Perl, DDR, Axi, Coresight, LPDDR, RTL, UltraSoC, Cadence Palladium, systemverilog, VHDL, Cadence Palladium XP, ZeBu

ARM Architecture Cortex-M7, Synopsys Zebu emulators, Logic Analyzer, T32 Debugger

Python Scripting, System Verilog, BFM models, GPU emulation

FPGA Design, Python Scripting, Soc Architecture, Test Automation, systemverilog, Verification Methodology, Hardware Debugging, Signal Integrity, Performance Analysis, Emulation Tools

Tcl, Verilog, System Verilog, C, Gdb, Python, Veloce, Zebu, waveform debuggers, Palladium

Perl, Verilog, Python, Tcl, Cadence Xcelium, Palladium, Rtl Design, Synopsys VCS, VHDL, Zebu, SoC Verification, Velloce

Perl, Verilog, Python, Tcl, Cadence Palladium, RTL, Digital Design, emulation compile mapping, systemverilog, acceleration, ASIC SoC emulation, UVM-based verification environments, Synopsys ZeBu, runtime concepts, partitioning