Perl, Verilog, Python, SoC Verification, Makefiles, fuse floorsweep design, RTL Build flows, Padring, Design Automation, Rtl Design, Physical Design, Synthesis, Dft, System-On-Chip design implementation flow, SOC integration, Chip Design

Unix, Python, Shell, Linux, Skill, SoC Integration, Rtl Design

pipelining , Perl, Verilog, Debugging, Python, Tcl, Synthesis, Timing Analysis, datapath design, digital IP development, systemverilog, Rtl Design, low-power design concepts

Sta, LINT, Memory operation, Synchronous design concepts, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, spyglass, Synthesis, device physics, CDC methodologies, Simulation verification

RDC, RTL coding expertise in Verilog, SpyGlass Lint, micro-architecture development, systemverilog, FSM design, Pipelining techniques, ASIC SoC design flow, Datapath architecture, cdc, Clock and Reset domain crossings