clocking , Ovm, DDR, Pcie, Verilog, Ethernet, Platform bring up in Emulators or Silicon, SOC boot flow, Constrained-random verification environments, Uvm, systemverilog, Power management flows, C SV tests, Low Power Verification, Coverage report generation, System Verilog Assertions, RTL GLS level simulations

Uart, Usb, Tcl, Ethernet, Perl, Spi, I2c, Shell Scripting, Python, DDR, AHB, UCIe, Siemens QuestaSim, Functional Coverage, systemverilog, MIPI, CXL, DVE, APB, Axi, Cadence Xcelium, Uvm, Constrained Random Verification, Scoreboards, Verdi, Functional Checkers, Synopsys VCS

Usb, Vcs, DDR, Pcie, Perl, Ethernet, Shell scripting, Python, Tcl, Xcelium, Uvm, systemverilog, Questa

Pcie, Ovm, Scripting, System Verilog, Ethernet, Uvm, HBM2, HBM3, Memory protocols, GDDRx, SVA, AHB, LPDDR4, AMBA standards, APB, High speed SerDes, Axi

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Version Control Systems, Computer Architecture, Soc Architecture, Simulators, coverage analysis, Formal Verification Techniques, Constrained Random Testing, PCIe Protocol Concepts, Advanced Debugging, Simulation Failures, Waveform Analysis, Root-Cause Identification, Functional Verification, Testbench Development, EDA Tools, Verification Planning, Rtl Design

Debugging, Uvm, Test Planning and Strategy, systemverilog, Mixed-Signal Verification

ARM M-series core operations, DMA interrupt handling, Debugging using disassembly and Tarmac for ARM cores, C code for ARM processors, UVM testbench development, Cache and interconnect, Cadence simulators and SimVision, Cadence and Synopsys VIPs, AHB and APB interface protocols