power optimization , Verilog, System Verilog, digital design principles, EDA Tools, Mentor Graphics, area trade-offs, Cadence, Timing Analysis, Synopsys

thermal management , ltspice , Orcad, MATLAB, Reliability Engineering, DC-DC Converters, Magnetics Design, Power Semiconductor Devices, Cadence, Simulink, Inverters, Analog and Digital Power Electronics, Psim, System architecture and requirements management, Simplis, Power Electronics, Saber, APQP Stage-Gate Product Development Process, Switching Power Supply Design, Ups Systems, Altium Designer, Design Reviews, Root Cause Analysis, Battery Chargers, PLECS, Dfmea, PFC Energy Storage Systems, Pfmea

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Soc, Verilog, Bus architectures, Logic synthesis for RTL code performance and power, Tape outs and bring up support, systemverilog, RTL design concepts, Memory hierarchies, Digital logic design principles, Accelerators, Processor design, Design implementation and integration of chassis subsystems, Arithmetic units, Low-power design

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation

Spectrum Analyzer, Signal Integrity and Power Integrity Analysis, Oscilloscope, Logic Analyzer, Analog and Digital Circuit Design, Network Analyzer, PCB Design and Layout Review, Signal Conditioning Circuits, Communication Protocols SPI I2C UART CAN RS-485 Ethernet, Hardware Debugging and Failure Analysis, Microcontrollers DSPs and FPGA Integration, LTspice PSpice, Power Supply Design, EMI EMC Design and Debugging, Mixed Signal Design Architecture, ADC DAC Interface Design

Static Timing Analysis (STA), Fpga, Synthesis, ASIC design flows and methodology, low power design implementation, power gating, sign-off optimizations, multi-voltage domains, deep sub-micron technology, Physical Design, IP integration, DSP systems, sign-off convergence, SOC place and route, Circuit Design, device physics

Coding Methodology, RTL Linting, Synthesis, Design Compiler, primetime, Timing Closure, Genus, SDC Constraints, Tempus, systemverilog