shielding , matching , Latch-up, parasitic analysis, SRAM Layout, yield and reliability issues, coupling, Electro-migration, crosstalk, CAD team, schematics interface, Circuit Design, IR-drop, design rules, layout area and routing optimization, advanced CMOS process

Pvs, Analog layout design, die-to-bump connectivity, package substrate interactions, R3D, PEX, analog layout matching techniques, EM, Ir, IC Layout design, LVS, CAD Tools, Floor Planning, Calibre, Xl, Esd, PowerFET, DRC, virtuoso, Packaging