VA VE implementation, Tolerance stack up analysis, Proof of Concepts prototyping and testing, CAD software, Dfmea, Plastic Design, Fluid mechanical concepts, Dfm, Design Calculations, SolidWorks PDM, New Product Development, DFA

tolerance analysis , Capability Studies, resins, Mechanical Aptitude, Fea, Injection Molding, engineering work plans, Plating, Metals, Product Design, electrical connector design, stamping, Dfmea, assembly, Doe, statistical methods

rtl development , Vcs, Gdb, Verilog, ASIC design flow, floor-planning, Timing Analysis, Logic Synthesis, Eco, design and verification tools, micro-architecture, Debussy, bring-up lab debug

tolerance analysis , Capability Studies, Fea, resins, Mechanical Aptitude, Injection Molding, engineering work plans, Plating, Metals, Product Design, electrical connector design, stamping, Dfmea, assembly, Doe, statistical methods

simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities

Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

accelerated life testing , Reliability Engineering, Design Verification Validation, DFMEA FMEA Facilitation, FTA RBD Weibull Analysis, Root Cause Analysis, Reliability Prediction Statistical Analysis, Functional Safety Concepts, Product Safety Engineering, EMC EMI Risk Assessment

Verilog, System Verilog, Digital Logic Design, Synthesis, Pre-Silicon Verification, Post-Silicon Support

Scripting, Flow automation, Foundation IP design, Cadence, Synopsys, Analog Design, IO standard cells, IP design kit preparation, NVM IP integration and troubleshooting, Automated IP onboarding and release flow, NVM IP benchmarking, NVM technology macro architecture and design, Memory design SRAM NVM, IP onboarding, Verification