Verilog, Fpga, VHDL, systemverilog, ASIC Design, Synthesis Tools, Timing Analysis, Verification Methodologies, Physical Design, low power design

Verilog, System Verilog, Sta, Synthesis, Physical Verification, CTS, Synopsys physical design tools, DFT tools, Extraction, Timing Analysis, Place And Route

Bias generators, Bandgaps, Simulation verification, Cadence Virtuoso Spectre, ADCs, SPICE-based simulations, Analog Circuit Design, Power-management ICs, DRC LVS extraction, MOSFET physics, DACs, Silicon debug support, Driver amplifiers, DC-DC converters, Post-layout verification, Sensing circuits, Gate drivers, Error amplifiers, Charge pumps, LDOs, Level shifters, Analog Layout

Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog

Verilog, System Verilog, Digital Logic Design, Synthesis, Pre-Silicon Verification, Post-Silicon Support

Ecos, Perl, Tcl, Python Scripting, Sta, CTS, Cadence Innovus, routing optimization, congestion optimization, SDC, MMMC, advanced technology nodes, full-chip physical implementation, constraint development, floorplanning, PPA improvements, Timing Analysis, setup hold closure, SI crosstalk, Timing Closure, complex SoC designs, Placement, Power Planning

Scripting, Flow automation, NVM technology macro architecture, NVM, Foundation IP design, Sram, Cadence, Synopsys, Analog Design, IO standard cells, Memory Design

transistor-level design and simulation, PEX, post-layout verification, LVS, noise analysis, Analog Circuit Design, Spectre, advanced CMOS technology nodes, DRC, layout sensitivity, linearity matching, mixed-signal IC design, Cadence Virtuoso