Perl, Python, SV, low power simulations, Uvm, testbench development, debugging gate level simulations, Axi, APB, BUS Protocols, assertions coding, AHB

Gdb, Verilog, Python, Perl, Indago, SV scripting languages, Cadence

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Uart, Usb, Regression Testing, C Programming, Ethernet, SVA, Assertions, Uvm, UPF, Functional Coverage, systemverilog, AMBA Protocols, AHB, CPF, APB, Axi, ARM-based SoC Verification

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Verilog, Gdb, Perl, Python, SV-UVM, e-specman, SV, Indago, Cadence, Verification fundamentals

Usb, Vcs, DDR, Pcie, Perl, Ethernet, Shell scripting, Python, Tcl, Xcelium, Uvm, systemverilog, Questa

Perl, Python, Formal Verification methodologies, Axi, APB, JasperGold, AMBA protocols, VC Formal, Uvm, AHB, systemverilog

Debugging, Uvm, Test Planning and Strategy, systemverilog, Mixed-Signal Verification