C, Pcie, Perl, Python, Tcl, ONFI, LPDDR, NAND

simvision , Tcl Scripting, Vcs, Pcie, Verdi, Xcelium, Uvm, systemverilog, APB, Questa, SVA assertion writing, AXI4, AHB, CDC verification, TLP handling

C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling

Pcie, Perl, Python, Tcl, protocol-level debugging, simulation and debug tools, verification methodology, UCIe, Uvm, FDI, systemverilog, coverage closure, CXL, RDI, SVA

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping

C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components