Pcie, Ethernet, Test Methodologies, Sta, AI-powered tools, Synthesis, gate level verification, Verilog RTL design, package and board design, UCIe, DFT flows

Jira, Pcie, SFDC, Ethernet, Test Methodologies, Sta, ADC, Tx and Rx Equalizers, Phase Locked Loops, Noise, board design, gate level verification, jitter, UCIe, case management systems, DFT flows, AI-powered tools, Synthesis, Verilog RTL design

HDL - Verilog, Logic Design, Perl, shell scripting, System Verilog, Tcl, Synthesis, formal verification, low power design, Physical Design, EDA Tools, Timing Closure, digital ASICs, Genus Synthesis Solution