HDL - Verilog, Logic Design, Tcl, shell scripting, System Verilog, Perl, Synthesis, EDA Tools, Genus Synthesis Solution, low power design, Cadence Tools, Physical Design, formal verification, Timing Closure

PERL, Tcl Scripting, EDA Tools, VHDL, synthesis concepts, HDLs Verilog, leakage and dynamic power optimization, low-power concepts, systemverilog, Process Automation, Rtl Design, Cadence