Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog

Synopsys tool suite, Synthesis and STA, IR EM analysis and resolution, physical design verification, ICV or Calibre tools, scripting languages like Tcl and Python, block level and full-chip physical verification methodology, block physical design PDV and IR, full chip floor-planning and integration, complete physical design flow, block subsystem timing closure

Tcl Scripting, Perl, Shell scripting, Python, CTS, primetime, Fusion Compiler, floorplanning, Tempus, Cadence Innovus, signoff, Power Planning, Physical Verification, routing optimization, Eco, Timing Closure, Placement, RTL-to-GDSII Physical Design flow, Synopsys ICC2

Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation

hardware engineering , Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, device physics, Low power design implementation

static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, Place And Route, low-power design techniques, Clock Tree Synthesis