power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout

Place and route (PnR), System on Chips (SoCs), Static Timing Analysis (STA), Unified Power Format (UPF), Deep sub-micron technology, Multi-voltage domains, Physical design methodologies, Circuit Design, Power gating, IP integration, Netlist2GDS, ASIC design flows, Sign-off optimizations, Multiple technology nodes in advanced processes, device physics, Floorplan, Sign-off convergence, Lower technology nodes, Low power design implementation

power optimization , Routing, Logic Design, Perl, Python, Tcl, Circuit Design, floorplanning, Mentor, Cadence, Signal Integrity, LVS, Digital Design Fundamentals, Physical Verification, Physical Design, ERC, Placement, Timing Closure, DRC, Timing, EDA Tools, Synopsys, Rtl Design

Coding Methodology, RTL Linting, Synthesis, Design Compiler, primetime, Timing Closure, Genus, SDC Constraints, Tempus, systemverilog

Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

thermal management , ltspice , MATLAB, Altium Designer, Oscilloscopes, Embedded control integration, Cadence, Simulink, Simulation analysis, Inverters, Power analyzers, Dfm, Power conversion circuits, DC-AC converters, PLECS, Pcb Layout, schematic capture, Protection circuits, EMI EMC mitigation, Dfmea, Thermal cameras, Analog digital interface design