Verification methodologies such as UVM, Understanding of StarRC Calibre parasitic extraction flow, NAND Flash memory design, Test Bench development in System Verilog

layout planning, nanometer CMOS, compiler usage, physical implementation, schematic capture, margin verification, Memory Architecture, variation-aware design techniques, characterization, Circuit Design, Simulation

Pcie, Ovm, Debugging, Unix Shell Scripting, Verilog, System Verilog, Perl, Tcl Scripting, DDR, Circuit Analysis, Uvm, IC chip design development flow process, CAE CAD tools, Circuit Design, test bench development, VHDL, AHB, Axi, CMOS logic design, coverage assertion driven verification, CMOS device operation and characteristics, verification plans, Simulation