Debugging, Perl scripting, Cadence Tools, Innovus, RTL2GDS, IP QA, Mentor Calibre, Apache RedHawk, Genus, Synopsys Prime Time, CMOS circuit design fundamentals

hardware engineering , Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation

redhawk , LVS, Power Grid Design, Antenna and IR Drop Analysis, Fusion Compiler, Physical Verification, Calibre, floorplanning, Innovus, Routing on lower technology nodes, Setup hold timing closure, End-to-end Place Route PnR flow execution from Netlist to GDSII, primetime, Voltus, ERC, Placement, DRC, IC Compiler II

Routing, Calibre, Tcl tool scripting, DDR design knowledge, primetime, EDA Tools, floorplanning, Innovus, Physical Design Methodologies, RTL-to-GDSII implementation, Placement, Genus, MultiTap-CTS

Physical Design, Physical Design Engineer, Automation script

Physical Design, Design for manufacturability, Timing closure methodologies, Placement and routing techniques, Clock Tree Synthesis, Design rule checks

Tcl, Python, PERL, Seahawk, Synthesis, ECO Timing Closure, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Physical Verification, Ir, CTS, Innovus, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Place And Route, Timing Convergence, High Frequency Design Methodologies