Statistical Analysis, Rom, characterization, Circuit Design, Mentor Graphics, Cadence, Sram, TCAM, Functional simulations, Synopsys, Silicon bring-up

SOC-level pattern retargeting, RTL-level DFT insertion, Siemens Tessent, Synopsys TestMAX, Cadence Modus, netlist handling, ATPG simulations, SpyGlass for DFT linting, TetraMax, Mixed-Signal DFT methodologies, PDL standards

Test Planning, Vcs, Jtag, Shell, Perl, Python, Tcl, GLS Signoff, Fusion Compiler, Xcelium, Silicon Bring-up, MBIST, Scan Insertion, Tessent, ATPG, Conformal Formality, DFT RTL Design Integration, Genus, Diagnosis, Debug, LBIST, IJTAG, DFT Architecture

boundary scan , logic bist , Test Automation, DFT Methodologies, Scan Design, Fault Simulation, ATE Programming, Design Debugging, DFT Architecture, Timing Analysis

AWS, Nltk, Python, Gcp, Azure ML, LangChain, Google AI Platform, Hugging Face, Haystack, SageMaker, CrewAI, Google Agents, LangGraph, spaCy