Scripting Language, python, Uart, test cases coding, SV, Uvm, IJTAG protocol, Axi, BUS Protocols, APB, Code and Functional coverage analysis, Test bench development

Verilog, Ovm, System Verilog, Synopsys VCS, Cadence IES, VMM, formal property checking tools, Uvm

Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Scripting, Verdi, IUS, Uvm, GLS, systemverilog, debug tools, Axi, IP SOC verification, Questa, CXL, CPU-based verification

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Usb, C, Debugging, Object Oriented Programming, Writing Test Cases, DDR, Ethernet, Perl, Pcie, Tcl, Function coverage, Coverage driven verification, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, Test bench development, CXL, Simulation, Eth

C, coverage closure, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Design Verification, Uvm, Verification Planning, systemverilog