System Verilog, WREAL, Spice, Uvm, functional tests, RNM, Co simulation RTL, verification test benches, Vams modelling, AMS Verification, RISC CPU, Analog blocks

Usb, Vcs, DDR, Pcie, Perl, Python, Tcl, Uvm, systemverilog, Axi, DVE, Modelsim, AHB

AI ML techniques, Uvm, systemverilog, Coverage-driven verification

System Verilog, chip design flow, constrained-random verification environments, design verification methodologies, hardware verification languages, Specman, ASIC standard interfaces, verification techniques, performance verification of ASICs, memory system architecture

Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Ovm, Test and coverage plan, Assertion checkers, System Verilog HVL, VMM Test Harness, Uvm, Validation plan, Coverage and scenario creation, Verification environment

System Verilog, Axi, dv methodologies and tools, ACE-Lite, Uvm, LPDDR5 protocols, Digital design concepts, Bus protocols like AHB, Ace, Debug

Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero