Usb, Mercurial, Svn, DDR, Git, Perl, Pcie, Ethernet, Python, Tcl, UVM methodology, AMBA, SoC level verification, UVM based verification environments, Design Verification infrastructure

Assembly Language, C, Ovm, PERL, Verilog, Shell script, System Verilog, Systemc, System Verilog PLI, Uvm, Emulation, Functional Verification, DPI interface, SoC Verification

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components

wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies