rtl development , nand flash , Tcl, Verilog, FPGA Design, Python, Bash, Pcie, IP Integrator, Vivado Design Suite, VHDL, ChipScope ILA, Embedded Systems, Xilinx FPGAs

Bash, Sql, FPGA Design, Git, Perl, Verilog, Rest Apis, Python, Tcl, radiant, CI CD tooling, RTL simulation tools, systemverilog, quartus, Vivado

Bluetooth, Usb, Spi, Iot, FPGA Design, Ethernet, Pcie, I2c, Ddr3, Microcontrollers, Wi-Fi, Microprocessor design, Sram, Power Electronics, Mixed signals, Electrical design engineering, Controls and Instrumentation, Electrical engineering design concepts, RTL design language, ETHERCAT

JIRA, Jenkins, Analyzing verification issues, Intel Quartus, Xilinx Vivado, FPGA design and verification following the DO-254 process, Interpreting schematics and layout diagrams, RTL design using VHDL, Electronic components and circuit design flow, Microchip Libero SoC

FPGA Design, Verilog, FPGA debugging, VHDL, AMD Vivado, logic analyzers, Intel Altera Quartus, Oscilloscopes, Libero SoC

Pcie, Verilog, FPGA Design, Correlation, Ethernet, Sta, Vitis, cdc, Intel Quartus, DSP fundamentals, SoC architectures, VHDL, FFT, SERDES, JESD204, multi-clock domains, AMBA protocols, Filters, Xilinx Vivado, Axi, RTL skills, APB, Timing Closure, AHB

Vcs, Pcie, Verilog, Debugging, Python, Scripting, Bash, Digital Logic Design, FPGA Design, Ethernet, Tcl, high-speed interfaces, Xcelium, Simulation Tools, FPGA synthesis, LPDDR4, Altera Quartus Prime Pro, LPDDR5, systemverilog, Axi, Timing Closure, Questa, CXL, DDR5, DDR4

Logical Partitioning, Debugging, FPGA design synthesis, RTL designs, FPGA HAPS, FPGA systems, Mapping