Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

Test Planning, Ovm, Debugging, CHI, Uvm, system simulation tools, AHB, UVM-based test benches, SoC design verification, APB, Axi, emulation models, AMBA protocols

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming