clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus

Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Signal Integrity, Leakage Power, Multi-Vt Flow, Dfm, IC design, Power Supply Management, Deep Sub-Micron Design Problems, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

Physical Design, Physical Design Engineer, Automation script

cadence encounter , Shell, Unix, Linux, Flow automation, Python Script, SDC STA and Equivalence checking, Tapeout sign-off experience, 10nm 7nm 5nm process nodes, Synopsys ICC2 tool set, Physical Design, PnR tools like ICC2 Innovus, Skill

Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, AI-assisted Tools, NDM Liberty, MemView Generation, LEF, PVT Corner Coverage

static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, low-power design techniques, Place And Route, Clock Tree Synthesis

NDM Liberty .lib, Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, MemView Generation, LEF, PVT Corner Coverage

Ecos, routing, Perl, Python, Tcl, Sta, Synthesis, Design Compiler, CTS, primetime, Fusion Compiler, floorplanning, Asic Physical Design, setup hold closure, Placement, MCMM timing analysis, Synopsys ICC2