PEX, analog mixed-signal IC design flows, deep-submicron advanced-node technologies, CMOS analog layout techniques, LVS, custom analog IC layout, layout methodology automation, parasitics, ERC, DRC, layout-dependent effects, Cadence Virtuoso, device physics

Analog Circuits behavior, Circuit Design concepts, Deep submicron process nodes, Layout Design for analog and mixed-signal blocks

Design for manufacturability and testing considerations, Analog Layout, Power distribution challenges, Parasitic Extraction, Analog circuit design principles

layout techniques for analog and mixed-signal circuits, Cadence Virtuoso Layout Editor VLE VXL, Mentor Graphics Calibre DRC LVS

CMOS, VLE/VXL, Analog Layout, Cadence, DRC/LVS, Mask Design