Analog Layout Engineer (4 - 9 Years )

Position: Junior/Senior Layout Engineer

Notice: Immediate

Location: Hyderabad

Experience: 4 - 9 Years

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Company Description SILCOSYS Solutions Pvt. Ltd. partners with leading global clients to develop their next-generation flagship products across mobile devices, networking equipment, consumer electronics, storage solutions, microprocessors, and graphics processors. The company focuses on pioneering cutting-edge technologies that are both pivotal and rare within the semiconductor industry. SILCOSYS is distinguished by deep expertise in designing highly complex System-on-Chip (SoC) solutions. It also maintains one of the industry's strongest analog/mixed-signal and software design teams, providing a dynamic environment for engineering professionals. Team members gain exposure to advanced design challenges and diverse product domains.

Role Description This is a full-time, on-site Analog Layout Engineer role based in Hyderabad, for professionals with approximately 4–9 years of relevant experience. The Analog Layout Engineer will be responsible for creating and optimizing layout designs for analog and mixed-signal circuits, ensuring proper matching, symmetry, and adherence to design rules. Daily activities include collaborating closely with circuit designers to interpret schematics, performing layout-versus-schematic (LVS) and design rule checks (DRC), and resolving physical verification issues. The role involves working with process technology files, applying best practices for parasitic-aware layout, and supporting tape-out activities. The engineer will also participate in design reviews, maintain documentation, and coordinate with cross-functional teams to meet project schedules and quality targets.

Qualifications

• Strong proficiency in layout-related skills, including Layout Design for analog and mixed-signal blocks.
• Solid understanding of circuit-related skills, including Circuit Design concepts and Analog / Analog Circuits behavior.
• Hands-on experience with Physical Verification, including LVS, DRC, and other sign-off checks.
• Experience with industry-standard EDA tools for analog layout (e.g., Cadence Virtuoso or similar) and familiarity with deep submicron process nodes.
• Bachelor's or Master's degree in Electronics, Electrical Engineering, or a related field.
• Ability to interpret specifications, work collaboratively with design and verification teams, and manage tasks independently under project timelines.
• Strong analytical skills, attention to detail, and commitment to quality in layout implementation.
• Prior experience in analog/mixed-signal SoC environments or similar product development settings is an advantage.