python, Signal Processing, Reliability Testing, weibull analysis, risk identification, random failure principles, ALt, Electronics, Measurement, statistical reliability analysis, reliability engineering, Bayes theorem, Test-to-Failure, FIT rate estimation methodologies, FMEDA, halt, ?²-statistics, reliability prediction, reliability calculations, Sensors, accelerated stress testing, FTA, environmental validation, HAST

Tableau, Tcl, Powerbi, Ms Excel, Python, PERL, Ccsp, Sta, AOCV, EDA development, Layout Design, FinFET technologies, Standard Cell Circuit Design, RTL2GDS flow, NLDM, Circuit and MC simulations, LVF, characterization, PNR, Layout Dependent Effects, Skill, CCSN

snowflake , ARM templates, Ms Azure, Django, Oauth, Gradle, Numpy, Hibernate, Python, Design Patterns, MS SQL, Azure Ad, Git, Rest Api, AKS, HD insight, Virtue Networks, Application gateway, Github Actions, Event Hub

Perl, Verilog, Python, Tcl, formal verification with Cadence LEC, Netlist CLP, Spyglass Lint CDC checks, UPF, clock domain crossing designs, Rtl Design, Synthesis, Logical Equivalence checks, low power design methodology

Ml, C, Python, Electromagnetic Design, Siemens Nx, Ai, Electromechanical design

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, SystemVerilog UVM, Axi, CXL, SVA

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC