Perl), scripting languages (TCL, boundary scan , Jtag, Python, Sta, RTL design and verification, SoC design flow, Scan Insertion, MBIST, Fault Models, ATPG, Timing Closure, IEEE 1149.1, LBIST, Compression

Debugging, Scripting, RTL Coding, ECO flows, LINT, formal equivalence, cdc

Verilog, System Verilog, RNM modelling, AMS Digital Block Modelling, dotlib generation, Formal verification methodologies, MSV simulation flow, Uvm

bandgap references , temperature sensors , Dll, Process Monitor, IO Buffers, Claude, Oscillators, verification processes, agentic AI models, design validation, Parasitic modeling, CMOS Amplifiers, modeling and simulation, Analog Test Mux, AI proficiency, LDOs, Charge Pumps, Comparators

Usb, Tcl, Verilog, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, ASIC design flow, Synthesis, LINT, peripheral IPs, Low-power design, Timing Analysis, Axi, BUS Protocols, MBIST, MIPS, Bus Matrix design, AMBA, Rtl Design, Timing constraint SDC, DFT concepts, Power estimations, RDC, Formal CDC