Staff Engineer Design
Staff Engineer Design
Infineon Technologies- Posted 17 hours ago
- Be among the first 10 applicants
Job Description
Candidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation.
Your Role
Key responsibilities in your new role
Candidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation.
MUST have:
Qualifications And Skills To Help You Succeed
[Confidential Information]
#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in
We are on a journey to create the best Infineon for everyone.
This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.
Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.
Click here for more information about Diversity & Inclusion at Infineon.
Your Role
Key responsibilities in your new role
Candidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation.
MUST have:
- Good understanding of modelling technique for Analog Blocks using Verilog and System Verilog.
- Good exposure on digital verifications,
- Ability to interact and work with team member in multiple geography.
- Good exposure to dotlib generation.
- Exposure to the MSV simulation flow.
- Basic understanding of analog circuits.
Qualifications And Skills To Help You Succeed
- BS/MS in Electrical Engineering
- Bachelor's - 6 to 11 years experience, Master's - 4 to 10 years experience.
- Very good knowledge of Verilog/System Verilog and UVM.
- Should be a good mentor and guide for junior engineers in the team.
- Candidate should have worked on AMS/Digital Block Modelling based RNM modelling.
- Exposure to deployment of automation and formal verification methodologies is a plus.
[Confidential Information]
#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in
We are on a journey to create the best Infineon for everyone.
This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.
Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.
Click here for more information about Diversity & Inclusion at Infineon.
More Info
Job Type:
Industry:
Employment Type:
Key Skills
RNM modelling
AMS Digital Block Modelling
dotlib generation
Formal verification methodologies
MSV simulation flow
About Company
Skills:
Usb, Tcl, Verilog, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, ASIC design flow, Synthesis, LINT, peripheral IPs, Low-power design, Timing Analysis, Axi, BUS Protocols, MBIST, MIPS, Bus Matrix design, AMBA, Rtl Design, Timing constraint SDC, DFT concepts, Power estimations, RDC, Formal CDC
Skills:
Test Planning, C, Systemc, Shell, Verilog, Tcl, Python, power-aware verification using UPF, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification
Skills:
C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator
Skills:
System Verilog, Python, Scala, Chisel, Uvm