Tcp, Ipv4, Perl, Pcie, Ethernet, System Verilog, Python, Gate Level Simulations, RDMA, vc formal, System Verilog constraints structures and classes, Palladium, Uvm, Emulation, Zebu, Veloce, iev, HAPS, formal verification

Perl, Python, System Verilog, Building test benches from scratch, Zebu, Veloce, ASIC verification using UVM, Palladium, HAPS

C, Linux, Python, Debugging, Windows OS, Automation Development, Protocol Analyzers, High-speed Lab Equipment, PCIe protocol standards, Device driver interactions, RAS feature set, BERT systems, x86 architecture, RDMA, Compliance Testing, Teledyne LeCroy, Oscilloscopes, VIAVI, Post-Silicon Validation

System Verilog, Gate Level Simulations, Building test benches, ASIC verification using UVM, formal verification

Perl, Python, System Verilog, Tcp, Pcie, Ethernet, Zebu, Veloce, Palladium, HAPS, Gate Level Simulations, RDMA, IPv4/6, Emulation, System Verilog constraints, Uvm, structures and classes

data link layer , PCIe PHY-MAC interface protocols, Physical Layer, flow control, CDC synchronizers, SerDes PHY, async FIFO, integrating PCIe hard IP controller, PnR constraints, CXL 1.1 2.0 or 3.0 protocol knowledge, reset sequencing, Transaction Layer, multi-clock-domain design, wrapper RTL, error handling, SystemVerilog RTL, clock crossing, PCIe power management, PCI-SIG certification process, PCIe architecture, Virtual Channels, PCIe compliance testing, TLP structure

Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification

testplan creation, PCIe Gen5, AMBA AXI, PIPE protocols, scripting knowledge, test scenario development, UVM based verification methodology, code coverage management, design spec reviews, testbench development, testbench architectures