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PCIe IP Validation Engineer

PCIe IP Validation Engineer

Capgemini
8-12 Years
Not Disclosed
  • Posted a day ago
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Job Description

Job Title:

PCIe IP Validation Engineer

Location: Bengaluru, Karnataka, India

Experience : 8 to 12 years

Role Overview:

We are seeking an experienced Post-Silicon Validation Engineer specializing in PCI Express (PCIe) technologies. In this role, you will transition next-generation silicon from the fab to production. You will debug complex hardware bugs, validate electrical and protocol compliance, and test PCIe IP performance in physical system environments.

Key Responsibilities:

  • Validation Strategy: Define post-silicon validation plans, test strategies, and coverage goals for the PCIe subsystem on reference boards and customer platforms.
  • Silicon Bring-Up: Lead first-silicon bring-up, initial power-on phases, and functional health checks for the PCIe IP block.
  • Protocol Debugging: Triage and isolate hardware, firmware, and software integration issues across all PCIe layers (Physical, Data Link, and Transaction).
  • Compliance Testing: Execute and automate official PCIe compliance test suites (e.g., PCI-SIG Gold Suite) to ensure formal industry certification.
  • Lab Execution: Use high-speed lab equipment to diagnose signal integrity and link training (LTSSM) issues.
  • Expertise in RAS feature set along with good exposure on x86 architecture
  • Automation Development: Build and maintain automated validation frameworks to scale test execution over variable PVT (Process, Voltage, Temperature) corners.
  • Exposure to RDMA or similar technologies is a plus

Preferred Qualifications & Skills:

  • Education: B.Tech/M.Tech in Electronics, Electrical, or Computer Engineering.
  • Experience: 8+ to 12+ years of hardware validation and lab debugging experience.
  • Lab Equipment: Hands-on mastery of high-speed Oscilloscopes, Protocol Analyzers (Teledyne LeCroy, VIAVI), and BERT systems.
  • Domain Knowledge: Deep understanding of PCIe protocol standards (Gen 4, Gen 5, or Gen 6), LTSSM, and equalization phases.
  • OS & Drivers: Strong understanding of Linux/Windows OS kernels, device driver interactions, and PCIe memory mapping (MMIO, DMA).
  • Scripting: Proficiency in Python or C/C++ for test script automation and hardware register manipulation.

Email : [Confidential Information]/ [HIDDEN TEXT]

More Info

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Key Skills

Automation Development

RDMA

Device driver interactions

RAS feature set

BERT systems

High-speed Lab Equipment

x86 architecture

Post-Silicon Validation

PCIe protocol standards

Teledyne LeCroy

VIAVI

Protocol Analyzers

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