Usb, Vcs, DDR, Perl, Pcie, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog, CXL, LPDDR, high-speed protocols

arm architecture , C, Ovm, Jtag, Perl, Verilog, Python, System Verilog, CPU architecture, interconnects, Uvm, power management techniques, debug architecture protocols, coherent fabrics, VHDL, SoC Verification, SVTB

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

C Programming, System Verilog, DSP Image RADAR processing, SOC Chip level Cluster Sub-System Verification, Interconnect NIC FlexNoC Cache Coherency, Uvm, Microcontroller and Microprocessor architecture, ARM Cores

DDR, Shell, Pcie, Perl, Python, JESD204B, Uvm, UPF, GLS, systemverilog, MIPI, Dft, USB3

rtl verification , Debugging, AMS IP Verification, AMS IP Integration, SoC-Level Verification, Sub-System Verification, PDL Test Case Development, Gate-Level Simulation, Timing Simulation, Virtual Tester Simulation, Tessent DFT, DFT Pattern Generation, Pattern Simulation, Testbench Bring-Up

Perl, Ovm, Vcs, Python, Tcl, Questa, Modelsim, Uvm, systemverilog

Regression Testing, Usb, Uart, C Programming, Ethernet, SVA, Functional Coverage, Uvm, UPF, Assertions, systemverilog, Axi, APB, AMBA Protocols, CPF, AHB, ARM-based SoC Verification

Vcs, DDR, Pcie, Usb, Ethernet, AHB, CHI, Xcelium, Uvm, UPF, coverage-driven verification, VIP integration and customization, LPDDR, low-power verification, Ace, Emulation, debug using industry-standard simulators, FPGA prototyping, systemverilog, constrained random methodology, Axi, AMBA, APB, Questa, CXL, CPF, IP and SoC level verification, high-speed protocols, SVA

shell scripting, Perl, Python, Tcl, mixed-signal design verification, Cadence Spectre simulation, Cadence Mixed-Signal Design Environment, SV UVM-based testbenches, VerilogAMS, behavioral modeling, systemverilog