arm architecture , ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, PCIe Controller PHY IPs and protocols, DDR protocols, emulation constraints, pre-silicon SoC verification, Memory Controller PHY IPs, performance verification

System Verilog, Functional safety tests, Connectivity Checking, Power-aware verification, coverage analysis, Gate-Level Simulations, Post-Silicon Validation, Uvm, Analog mixed-mode AMS simulations, Coverage-driven verification, Fault injection simulations, AMBA bus protocols, Functional assertions, RTL Gate level verification, Axi, formal verification, APB, ISO 26262, TB development, Module level verification plan development, Property Checking, AHB, SoC Verification

Ovm, Debugging, Test Planning, CHI, SoC design verification, AMBA protocols, Uvm, UVM-based test benches, system simulation tools, Axi, APB, emulation models, AHB

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

SoC Verification, systemverilog, universal verification methodology

Low Power Verification., C Programming, SoC Verification, systemverilog, Uvm, ARM SoC, Gate Level Simulation, Coverage Closure, APB, AHB, Axi

Debugging Tools, Tcl, Python, Perl, LPDDR5, DDR4, Uvm, DDR protocols, DDR5, systemverilog, AHB, LPDDR4, Axi, DDR verification

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

C, Uart, Bash, Spi, Pcie, Perl, Verilog, I2c, Python, Tcl, i2s, DFX Verification, Uvm, systemverilog, Axi, APB, LPDDR, AHB