Python, Isaac SIM, Robotics simulation, Synthetic Data AI Integration, NVIDIA Omniverse, Microsoft Azure IoT, CuOpt Optimization, Robotics Factory Automation, Quality Analytics

Scripting, Odata Services, Abap Programming, Amdp, Node.js, Sap Fiori, Adobe Forms, CDS Modelling, Abap debugging, CAP microservices, rap, Abap Object Oriented programming, classical ABAP, SAP CAP, CDS S4HANA, SAP S4 Hana Abap, Change Master, UI5 development

scripting Python, structural FEA analysis, APDL, vibration impact shock fatigue, FEA tools such as ANSYS, nonlinear material structural response, ABAQUS

Apis, concurrency, Sql, flow logic, table relationships, Power FX expressions, Azure resources, end-to-end automation workflows, loops, ALM in the Power Platform, solutions environment strategy, Dataverse data modeling, Power Automate Cloud Flows, conditions, error handling, Power Apps Canvas, Microsoft Copilot Studio, security roles

Data Management, Service Cloud, Sales Cloud, Flows, APEX, Agentforce, Process Automation, Experience Cloud

Git, Linux Shell Scripting, Terraform, Docker, Datadog, Kubernetes, Python, AWS, Kustomize, CI CD

Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero

Doors, Tcl Scripting, FPGA Synthesis Place and Route, DO-254 development process, RTL development using VHDL, Hardware system design knowledge of digital logic, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, FPGA design tools like Libero, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory

Ui Ux Design, Sharepoint Online, Power Automate, Power Platform, Css3, React, Microsoft 365, Javascript, Html5, SPFX, Bootstrap, Restful Apis, Power Apps, Azure App Services, workflow automation, Teams, Copilot Studio