AI ML techniques, Uvm, systemverilog, Coverage-driven verification

Verification methodologies such as UVM, Understanding of StarRC Calibre parasitic extraction flow, NAND Flash memory design, Test Bench development in System Verilog

C, coverage closure, microprocessor ISA, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog

DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, SystemVerilog UVM, Axi, CXL, SVA

C, coverage closure, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design