Perl, Python, UVM based verification environments, Verdi or equivalent debug tools, systemverilog

wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

AI ML Accelerators, functional coverage, systemverilog, SVA, vector processing units

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

Verilog, System Verilog, Asic verification, Uvm, cpu design, DDR4, Memory