Arm, Python, RTL simulation, Debug, functional coverage closure, RISC-V, regression automation, x86 architecture, Uvm, SVA, systemverilog

occ, Memory-BIST, DFT architecture scan Insertion compression at core level and SoC level, SSN architecture, timing and no-timing simulations, clock architecture, ATPG pattern generation coverage analysis

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

UNIX, Debugging, Verilog, Windows, System Verilog, Digital IP development, RTL Coding, Automated flows for generating RTL

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

C, Python, Noc, RTL simulation, Emulation, debug methodologies, AMBA protocols, Uvm, systemverilog, power-management technologies

Perl, Python, Formal Verification methodologies, Axi, APB, JasperGold, AMBA protocols, VC Formal, Uvm, AHB, systemverilog

simulator , compiler , C, Verilog, Arm, Python, System Verilog, Embedded C Verification, Assembler, Floating point instructions implementation verification, RISC-V, Uvm, Logic Verification, processor toolchains, functional processor simulators