PERL, Tcl, Sta, Synthesis, CTS, Place Route, Full-chip Floor-planning, RTL2GDSII flow, ICC2, Physical Verification, Tempus, Make scripting, layout closure, timing convergence, primetime, Innovus, Physical Design, Timing Closure, high frequency design methodologies

Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC

Routing, Static Timing Analysis, Low Power Synthesis, Signoff, Low Power Designs, Logical Physical Aware Synthesis, High-performance digital designs, Power Signoff, Advanced low power design techniques, UPF, Custom ASIC flows, Synthesis, Physical Verification, formal verification, Placement, Clock Tree Synthesis, CPF, Floorplan

routing, physical design flows, digital VLSI concepts, Tempus, floor-planning, Cadence Innovus, Voltus, Timing Closure, EDA Tools, Placement, Logic Synthesis, Rtl Design

Static Timing Analysis, routing, chip finishing, LVS, clock-tree synthesis, Dfm, Physical Verification, DRC, Floorplan design, congestion reduction techniques, Low Power implementation, hierarchical designs, parasitic extractions, sign-off requirements, Synthesis, placement guidelines, place route flow, timing optimizations

Linux Scripting, Python, AI GenAI systems, VLSI EDA tools, Agentic AI MCP RAG workflows, triaging and debugging complex software tool issues