Perl, Python, Tcl, Emulation, systemverilog, System Verilog Assertions

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

C, Gdb, Python, Systemc, Emulation, qemu, Intel Simics, Simics Debugger

C, Verilog, Gdb, System Verilog, Python, Tcl, Zebu, Veloce, Palladium, waveform debuggers

System Verilog, Veloce, Zebu, Palladium, Hardware emulation platforms

DDR, Automation Frameworks, Ethernet, emulation methodologies, hardware software co-design, emulation testbenches, emulation models, PCIe protocols, ARM Cores, FPGA architecture

Pli, Systemc, ProtoCompiler, hardware emulation, Cadence Z3, Simulators, Siemens Veloce, FPGA prototyping, Xilinx Vivado, Synplify Premier, Synopsys ZeBu, SV Verilog, Emulators, dpi

Tcl, Verilog, System Verilog, C, Gdb, Python, Veloce, Zebu, waveform debuggers, Palladium