advanced matching and layout techniques, DRC LVS ERC and PEX, Cadence Virtuoso Custom Compiler, FinFET advanced-node layout, lower-node technologies, Analog Mixed-Signal Layout, MOS resistor capacitor current mirror differential pair and analog IP layouts

Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology

Cadence Virtuoso Layout Editor, Verification Tools, Cadence LVS, Calibre RVE

Synopsys, analog and mixed-signal AMS design, Analog Layout, LVS, Mentor Graphics, Cadence Virtuoso, DRC, post-layout simulation

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

matching , Bandgap Oscillators, xACT, LVS, EM, IR drop, Cadence Tools, parasitic effects, MXL, reference circuits, LVS DRC PEX EMIR verification flows, Quantus, GXL, EXL, Xl, Voltus, Calibre DRC, LDOs, StarRC

Multi-patterning, Device orientation matching, FinFET process nodes, Analog Mixed-Signal Layout, Parasitic Extraction, Signal Integrity, Design rules, Layout automation and APR methodologies

Cadence Tools, FinFET process technologies, DRC LVS checking flows with Calibre

Tcl, Perl, Skill, EDA Tools, Cadence Virtuoso