layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs

Fpga, Perl, Python, object-oriented design, RTL, test plan development, emulation platforms, Uvm, systemverilog, automation scripts

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

testability , systemverilog, SoC IP verification methodologies, Uvm, DFX DFT concepts, ATPG, multi-level verification

display technologies , Python Programming, Functionality, Bit Depth Color, OS Ecosystems, MIPI DSI-2, Bitstream Verification, Introspect SV series systems, Scaling Processing, FPGA Prototyping, PVT Testing, Frame Buffer, Lab Instrumentation, Pixel Formats, SV UVM, Continuous Integration tools, Low-Level Software