arm architecture , ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, PCIe Controller PHY IPs and protocols, DDR protocols, emulation constraints, pre-silicon SoC verification, Memory Controller PHY IPs, performance verification

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Low Power Verification., C Programming, SoC Verification, systemverilog, Uvm, ARM SoC, Gate Level Simulation, Coverage Closure, APB, AHB, Axi

Debugging Tools, Tcl, Python, Perl, LPDDR5, DDR4, Uvm, DDR protocols, DDR5, systemverilog, AHB, LPDDR4, Axi, DDR verification

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Perl, Verilog, Python, advanced verification methodologies like e-specman SV-UVM, debug tools like Indago GDB, SV scripting languages, Cadence or equivalent simulation tools